ASIC Design Engineer – Valencia

21-02-2019
Spain
IT
Technology
Telecomm.

For one of our clients, Melt Group is looking for an ASIC Design Engineer for Design Center in Valencia. In this role, you will be responsible for the architecture, design, verification, implementation, and post silicon validation of large scale deep submicron SoC projects.

The ideal candidate will have an ASIC design background with hands-on experience in RTL, verification and implementation, in-depth knowledge of SoC development cycle and best industry practices, and a proven track record of success in high-performance/high-volume semiconductor markets.

Responsabilities:

  • Works with cross-functional project teams to define product specifications, system architecture, HW/SW partitioning, and development plan;
  • Delivers chip/subsystem/block architecture, design, integration, verification, FPGA prototyping, implementation, and hand-off to backend. Validates the design, supports system integration, and brings the chip to production.

Required Experience:

  • Experience in SoC, embedded CPU and bus architectures, networking and control interfaces;
  • Experience in Communications/DSP and packet processing architectures, and efficient implementations;
  • Experience in low power and high speed design architectures, implementation trade-offs, and design for test (DFT);
  • Hands on experience in RTL design, simulation and verification methodology, Lint/CDC, tools and languages. C/SystemC, SystemVerilog and UVM knowledge is a plus;
  • Hands on experience in synthesis, equivalence checking, STA, timing closure, and power analysis in Cadence/Synopsys design environments;
  • Experience in FPGA emulation, lab debug and silicon validation;
  • Experience in UNIX and strong scripting capabilities, Perl, TCL, shell, etc;
  • Self-motivated, team building, and excellent communication skills;
  • Masters’ degree and 5 years of experience in ASIC/VLSI design.